FIG. 1 shows a typical computer system 100. The computer 100 includes a central processing unit (CPU) 105, or processor, and a memory repeater hub 110 (“memory unit” 110). A memory control unit (MCU) 120 controls the flow of data into and out of the memory unit 110. The memory unit 110 always includes volatile memory, such as dynamic random access memory (DRAM). The computer also includes other system components, including a non-volatile storage device, such as a hard disk 125, and a modem 130 to connect the computer 100 to a network 135. A bus 115 connects the components 105, 120, 125 and 130 of computer 100, allowing data and/or commands to be transferred between the components.
The speed at which the computer operates depends in large part on the speed at which data is transferred between the processor 105 and the memory unit 110. One memory architecture in particular, known as the RAMBUS™ architecture, is designed to transfer data to the processor 105 at very high rates, e.g., 1.6 GB/s for a typical RAMBUS™ DRAM (RDRAM) module.
FIG. 2 shows a common routing configuration for signal lines connecting the MCU 120 to the memory unit. Each signal line 150 leaves the MCU 120 with a width of approximately 18 mils. Before reaching the appropriate pin 155 on the memory unit, the signal line 150 narrows, or “necks down”, to a width of approximately 5 mils. The signal line 160 exiting the pin 155 also has a width of approximately 5 mils before expanding to a width of approximately 18 mils. A ground trade 165 separates the 5 mil neck down portions of the signal lines 150, 160. As a result of this congestion, the signal line 150 into the memory unit and the signal line 160 out of the memory unit often must be formed on different layers of the circuit board on which the MCU and memory unit reside.